Interrupt enable set register
| INX_INT | Writing a 1 enables the INX_Int interrupt in the QEIIE register. |
| TIM_INT | Writing a 1 enables the TIN_Int interrupt in the QEIIE register. |
| VELC_INT | Writing a 1 enables the VELC_Int interrupt in the QEIIE register. |
| DIR_INT | Writing a 1 enables the DIR_Int interrupt in the QEIIE register. |
| ERR_INT | Writing a 1 enables the ERR_Int interrupt in the QEIIE register. |
| ENCLK_INT | Writing a 1 enables the ENCLK_Int interrupt in the QEIIE register. |
| POS0_INT | Writing a 1 enables the POS0_Int interrupt in the QEIIE register. |
| POS1_INT | Writing a 1 enables the POS1_Int interrupt in the QEIIE register. |
| POS2_INT | Writing a 1 enables the POS2_Int interrupt in the QEIIE register. |
| REV0_INT | Writing a 1 enables the REV0_Int interrupt in the QEIIE register. |
| POS0REV_INT | Writing a 1 enables the POS0REV_Int interrupt in the QEIIE register. |
| POS1REV_INT | Writing a 1 enables the POS1REV_Int interrupt in the QEIIE register. |
| POS2REV_INT | Writing a 1 enables the POS2REV_Int interrupt in the QEIIE register. |
| REV1_INT | Writing a 1 enables the REV1_Int interrupt in the QEIIE register. |
| REV2_INT | Writing a 1 enables the REV2_Int interrupt in the QEIIE register. |
| MAXPOS_INT | Writing a 1 enables the MAXPOS_Int interrupt in the QEIIE register. |
| RESERVED | Reserved. Read value is undefined, only zero should be written. |